As VLSI technology continues to scale down, more and more complex signal processing algorithms such as Low-Density Parity-Check (LDPC) coding, MIMO detection, and Maximum Likelihood Sequence Estimation (MLSE) are integrated into a single chip to improve the system performance, which usually lead to large power consumption and hardware cost. On the other hand, the desire for high data-rate communications such as 100Gb Ethernet, low packaging cost,  and long battery life for wireless or portable devices has continued to increase. Thus VLSI design optimization for modern digital communication systems has become more and more critical.

In this talk, following a brief overview of CMOS IC design basics, three major optimization goals, i.e., low power, high speed and low latency, will be addressed. Generic techniques as well as commonly used application-specific design methods for each optimization target will be briefly discussed. Instead of explaining these fundamental techniques in detail, the talk will be focused on illustration of some state-of-the-art designs for each design objective.

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海报：VLSI Design Optimization for Signal Processing.pdf