Title: Modular Testing of Core-Based System-on-Chip Integrated Circuits

By Prof. Chakrabarty from Duke University

Time: 10:00am, Aug. 10, 2006.

Place: Room 125, FIT Building, Section 3

Abstract: The popularity of system-on-chip (SOC) integrated circuits has led to an unprecedented increase in test costs. This increase can be attributed to the difficulty of test access to embedded cores, as well as long test development and test application times. This talk will present test resource partitioning techniques that facilitate low-cost SOC test. Topics to be covered include techniques for modular testing of digital, mixed-signal, and hierarchical SOCs. Test planning methods that involve the use of wrappers and test access mechanisms will be discussed. Test scheduling techniques for the concurrent testing of embedded cores at the SOC level will also be presented. Finally, recent work on wafer-scale test planning will be discussed. Together, these techniques offer SOC integrators with the necessary means to manage test complexity and reduce test costs.

*KRISHNENDU CHAKRABARTY*

Prof. Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively, all in Computer Science and Engineering. He is now with the department of Electrical and Computer Engineering at Duke University. Prof. Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award and the Office of Naval Research Young Investigator award. His current research projects include: design and testing of system-on-chip integrated circuits; design automation of microfluidics-based biochips; microfluidics-based chip cooling; distributed sensor networks. Prof. Chakrabarty has authored three book: Microelectrofluidic Systems: Modeling and Simulation (CRC Press, 2002), Test Resource Partitioning for System-on-a-Chip (Kluwer, 2002), and Scalable Infrastructure for Distributed Sensor Networks (Springer, 2005), and edited the book volume SOC (System-on-a-Chip) Testing for Plug and Play Test Automation/ (Kluwer, 2002). He is also an author of two forthcoming books (to be published by CRC Press and Springer, respectively) on microfluidics-based biochips. He has published over 220 papers in archival journals and refereed conference proceedings. He holds a US patent in built-in self-test and is a co-inventor of a pending US patent on sensor networks. He is a recipient of best paper awards at the 2005 IEEE International Conference on Computer Design and 2001 IEEE Design, Automation and Test in Europe (DATE) Conference. He is also a recipient of the Humboldt Research Fellowship, awarded by the Alexander von Humboldt Foundation, Germany.

Prof. Chakrabarty is a Distinguished Visitor of the IEEE Computer Society for 2006-2007 and a Distinguished Lecturer of the IEEE Circuits and Systems Society for 2006-2007. He is an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on VLSI Systems, IEEE Transactions on Circuits and System I, ACM Journal on Emerging Technologies in Computing Systems, and an Editor of Journal of Electronic Testing: Theory and Applications (JETTA). He is a member of the editorial board for Microelectronics Journal, Sensor Letters, nd Journal of Embedded Computing, and he serves as a subject area editorfor the International Journal of Distributed Sensor Networks. In the recent past, he has also served as an Associate Editor of IEEE Transactions

on Circuits and Systems II: Analog and Digital Signal Processing. He is a senior member of IEEE, a member of ACM and ACM SIGDA, and a member of Sigma Xi. He serves as Vice Chair of Technical Activities in IEEE's Test Technology Technical Council, and is a member of the program committees of several IEEE/ACM conferences and workshops. He is the chair of the emerging technologies subcommittee for the IEEE Int. Conf. CAD (2005-2006), and subcommittee for new, emerging, and specialized technologies for the 2006 /IEEE/ACM/ /Design Automation Conference. He served as Tutorials Chair for the 2005 IEEE International Conference on VLSI Design and Program Chair for the 2005 IEEE Asian Test Symposium. He is the designated Program Chair for the CAD, Design, and Test Conference for the 2007 IEEE Symposium on Design, Integration, Test, and Packaging of MEMS/MOEMS (DTIP'07). He delivered a keynote speech at the International Conference & Exhibition on Micro Electro, Opto, Mechanical Systems and Components, held in Munich, Germany, in October 2005, as well as invited talks on biochips CAD at several other conferences.