Architecture-Aware Design of Signal Processing and Communication Algorithms
报告人:
Chaitali Chakrabarti
Professor in the Department of Electrical Engineering at Arizona State University, USA
报告时间:
2007-10-16 10:00
报告地点:
FIT 1-312
主办单位:
计算机系
简介:
Abstract: Traditionally, signal processing and communication algorithms have been designed with no thought given to the efficiency of their implementation on hardware platforms. This has resulted in inefficient implementations which could have been avoided had the algorithms been tailored to match the constraints imposed by the existing architecture. We illustrate the concept of architecture-aware algorithm design through two examples. In function evaluation on an FPGA platform, we show how algorithmic innovations in data reorganization and type of interpolation help meet the architectural constraints (memory size, number of slices). Next, in LDPC implementation on a multiprocessor platform, we show how architectural constraints can be mapped to code design constraints that can be utilized to construct architecture-aware LDPC code. We demonstrate how this procedure results in an efficient implementation for the case when the processor has limited memory.
Speaker: Chaitali Chakrabarti is a Professor in the Department of Electrical Engineering at Arizona State University, USA. Her research interests are in the areas of VLSI architectures for signal processing and communications, software defined radio, algorithm-architecture codesign, low power algorithm design, embedded system design including those powered by fuel cell -battery hybrid power sources. She is the Chair of the Technical Committee on Design and Implementation of Signal Processing Systems, IEEE Signal Processing Society. She was an Associate Editor of the IEEE Transactions on Signal Processing (1999-2004) and currently serves as the Associate Editor of the Journal of VLSI Signal Processing Systems and the IEEE Transactions on VLSI Systems.
