Albert Chin received the Ph.D. from the Department of Electrical Engineering, University of Michigan, Ann Arbor, in 1989.

He was with AT&T Bell Labs (1989~1990), General Electric- Electronic Lab (1990~1992) and visited Texas Instruments Semiconductor Process & Device Center (1996~1997). He has been a professor, vice executive officer of diamond project and deputy director of National Chiao Tung University, and a visiting Professor at National University of Singapore (2002~2006).

He is a pioneer of low DC-power high-κ CMOS, high-κ Flash memory, high mobility Ge CMOS, low AC-power 3D IC, high RF power asymmetric-MOSFET, and resonant-cavity photo-detector. He co-authored >450 papers and 7 Highly Cited Papers (top 1% citation). He served as panelist in Device Research Conf. (DRC), IEEE Si Nanoelectronics Workshop (SNW), IEEE ICSICT etc, given tutorial in Material Research Society (MRS), and delivered invited talks in major device conferences including premier Intl Electron Devices Meeting (IEDM). His high-κ CMOS, Ge CMOS and Flash memory were also cited by Intl Technology Roadmap for Semiconductors (ITRS) www.itrs.net.

Dr. Chin served as the Subcommittee Chair, Asian Arrangements Co-Chair and Chair of IEDM Executive Committee and Distinguished Lecturer of IEEE Electron Device Society. He is an IEEE Fellow and Optical Society of America Fellow. He currently serves as Editor of IEEE Electron Device Letters.

The IC chips have been widely used but also consume huge energy globally. To increase the IC speed, the MOSFET needs to deliver higher current by increasing inversion charge Q_inv (=C×V=ε_oκ/t_ox×V). The scaling oxide thickness (t_ox) has reached an ultra-thin ~1.2-nm in 65-nm node CMOS at year 2003, which causes very high gate leakage and DC power (P_DC) consumption.

To address this issue, we pioneered high high-κ gate dielectric CMOS at 1998, since higher Q_inv is also reachable by using high-κ dielectric. However, the unwanted high transistor V_t is the major challenge. Using unique + and - dipole charges of high-κ La₂O₃ and Al₂O₃, low V_t n- and p- MOSFETs were achieved at 0.6~0.9 nm EOT. Our pioneered La₂O₃ and Al₂O₃ high-κ dielectrics have been implemented in 32-nm gate-first CMOS manufacture by IBM alliance (IBM, Samsung, Global Foundries etc). Here the P_DC is lowered as high as ~2 orders of magnitude to save energy.

To further lower the AC switching power (P_AC) of CV_d²/2, we invented the high-mobility defect-free Ge-on-Insulator MOSFET on Si substrate. The 2.5X and 1.4X higher hole and electron mobility were reached in Ge p- and n-MOSFETs at 1~1.4 nm EOT that enable the low P_AC Ge CMOS at reduced V_d. The P_AC can be further lowered by our initiated 3D IC, using Ge CMOS on Si IC. A major equipment vendor is working to commercialize the Ge CMOS tools.

Low P_AC non-volatile memory is also required for IC function. Applying high-κ dielectrics into flash memory, fast write 100-μs and low ~10-V operation were reported by us, with 20X lower energy consumption than conventional flash memory. Our high-κ flash memory was listed in the Intl. Technology Roadmap for Semiconductors www.itrs.net as the enabling technology to down-scaling the flash memory into 1X-nm. At present, the high-κ flash memory has been successfully implemented at 20-nm 128 Gb flash memory manufacture.