As the technology node shrinks down to 45 nm and below, high power becomes one of the major critical issues for CMOS high-speed computing circuits (e.g. logic and cache memory) due to the increasing leakage currents and large data traffic. Emerging non-volatile memories are under intense investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its quasi-infinite endurance, high speed and easy 3D integration at the back-end process of CMOS IC fabrication, Spintronics (Nobel Prize 2007) memories such as STT-MRAM and Racetrack Memory are considered the most promising candidates. A number of hybrid Spintronics/CMOS computing circuits have been proposed and prototyped successfully in the last years. This talk presents an overview and current status of these logic circuits and discuss their potential applications in the future.