内容简介：

In this talk, the potential for bulk CMOS, SOI CMOS, and double-gate CMOS to extend scaling to 10 nm channel length is assessed.  In addition to the required replacement of silicon dioxide and polysilicon gates by high-k insulator and metal gates for all device types, specific technology requirements are discussed for each device type.  10 nm bulk CMOS requires abrupt placement of n- and p-type dopants at >10¹⁹ cm^-3 levels for both the channel and the source-drain regions.  10 nm SOI CMOS requires the silicon film thickness to be scaled to its quantum limit of 2 nm.  The silicon film thickness requirement is somewhat relaxed in a double-gate device structure.  But the self-alignment requirement of a double-gate (or multi-gate) device makes it very challenging to realize a manufacturable process.  It remains a challenge to ultimately scale CMOS technology to 10 nm.

报告人简介：

Yuan Taur received the Ph.D. degree in physics from University of California, Berkeley. From 1981 to 2001, he was a Research Staff Member with IBM Thomas J. Watson Research Center, Yorktown Heights, New York.  Since October 2001, he is professor in the Department of Electrical and Computer Engineering, University of California, San Diego.  Dr. Taur is elected a Fellow of the IEEE in 1998.  He is currently the Editor-in-Chief of IEEE Electron Device Letters, and Program Chairman of 2002 Symposium on VLSI Technology.  Dr. Taur’s current research interest is in advanced CMOS devices and their scaling limits.  He co-authored a book, “Fundamentals of Modern VLSI Devices,” published in 1998.