----- Abstract ------

At present, multicore processors are identified as the most viable
technology to continuously push processor performance for a reasonable
power and thermal budget, and are on the roadmap of almost every major
computer vendor. However, even though parallel processing has been
around for more than three decades, the challenges to create parallel
programs are still as daunting as they were then, and these challenges
are exacerbated by the power and thermal constraint in multicore designs.
While emerging technologies, such as 3D die stacking, can potential
mitigate some of the design conflicts, the impact of these technology
on architecture design is still unclear. Furthermore, improving processor
performance is not the only design goals for today's system designer.
The increasing sophistication of software systems and their execution
environment in multi-core systems makes it possible to support for
software programmability, testability and dynamic performance tuning.

In this talk, I first present our continuous effort in parallelizing
general-purpose applications. Under the context of Thread-Level
Speculation (TLS), our group is: implementing compiler optimizations
to utilize information from a variety of sources to conduct risk-benefit
analysis and code optimization; developing compiler and hardware supports
to dynamically monitor and evaluate the effectiveness of speculative
execution, and use the results to adjust speculation aggressiveness at
runtime; simultaneously discovering parallelism at several different
granularities; and ensuring that the proposed optimizations are power
and thermal efficient.

I will then briefly discuss a monitoring framework that improves the
programmability, testability and debuggability of software systems by
facilitating the specification and creation of low-overhead program
execution monitors. The framework has three key components: (i) hardware
support that enables monitoring the internal states of an application
with minimal performance impact; (ii) compiler support for generating
applications, monitors, and the means of orchestrating the proposed
monitoring hardware; and (iii) flexible programming language support
for satisfying a wide variety monitoring activities. Finally, I will
briefly outline our investigation on architecture-level innovations
that utilize 3D integrated circuits, taking into consideration the
on-chip power dissipation and thermal hotspot creation.

----- Antonia's bio: ------

Antonia is an assistant professor in the Department of Computer Science
and Engineering at the University of Minnesota. She received her Ph.D.
degree in Computer Science from Carnegie Mellon University in 2005 for
her research on developing advanced compiler technologies to exploit
the potential of thread-level speculation for general-purpose
applications. Prior to that, she received her B.A.Sc. and M.A.Sc. Degrees
in Computer Engineering from the University of Toronto in 1996 and 1998
respectively. She is interested in developing novel compiler optimizations
and architecture features not only to improve the performance for such
processors, but also to enhance non-performance features, such as
programmability, security, testability and reliability.

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Group of System Software and Software Engineering
Department of Computer Science and Technology
Tsinghua University