Addressing Challenges of VLSI Structural Testing

K.-T. Tim Cheng, Univ. of California, Santa Barbara and Univ. of Tokyo

As Design-For-Testability (DFT) techniques have become widely accepted and have achieved great improvements in product quality, these structural techniques have also introduced new challenges for testing complex nanometer devices. In this talk, I will discuss these challenges and present some of our recent research results addressing such challenges. Specifically, I will discuss the concept of pseudo-functional testing and present methods for generating pseudo-functional tests. I will further illustrate a unified approach to test generation, test stimulus compression, and test response compaction. Finally, a highly efficient diagnostic test generation framework which is based upon a Boolean Satisfiability engine will be presented.

Biography

Tim Cheng received the Ph.D. degree in Electrical Engineering and Computer Science from the University of California, Berkeley in 1988.

He worked at Bell Laboratories in Murray Hill, NJ, from 1988 to 1993 and joined the faculty at the University of California, Santa Barbara in 1993 where he is currently Professor of the Electrical and Computer Engineering Department. He was the founding director of UCSB's Computer Engineering program from 1999 to 2002 and Chair of the ECE Department from 2005 to 2008. He is currently visiting Univ. of Tokyo, Japan as Professor at VLSI Design and Education Center. His current research interests include design verification, test, silicon debug, and multimedia computing. He has published over 300 technical papers, co-authored four books and holds 11 U.S. Patents in these areas. Cheng serves on the Executive Committee of the MARCO/DARPA Gigascale System Research Center (sponsored by the Semiconductor Industry Association, U.S. semiconductor equipment, materials, software and services industries, and the U.S. Dept. of Defense) and Co-Director of the International Center of System-on-Chip and International Center on Design for Nanotechnologies (jointly sponsored by National Science Foundation, USA and Chinese National Science Foundation, China) and leading their design, test and verification research efforts.

Cheng, a fellow of IEEE, received Best Paper Awards at the 1994 Design Automation Conference and 1999 Design Automation Conference, 2001 Annual Best Paper Award in Journal of Information Science and Engineering, Best Paper Award in 2003 Conference of Design Automation and Test in Europe (DATE 2003), and the Best Paper award at 1987 AT&T Conference on Electronic Testing. He received the UCSB College of Engineering Outstanding Teaching Faculty Award in 2004-2005. He currently serves as Editor-in-Chief for IEEE Design and Test of Computers, Editor for IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Associate Editor for ACM Transactions on Design Automation of Electronic Systems, Associate Editor for Formal Methods in System Design, Editor for Journal of Electronic Testing: Theory and Applications, and Editor for Foundations and Trends in Electronic Design Automation. He has been General Chairs and Program Chairs for a number of international conferences on design, design automation and test.