Abstract:

Energy efficiency is one of the most critical design constraints for systems from portable devices to sensor networks and large data centers. As the technology continues scaling down, leakage power has become the dominant source for system's energy dissipation. Dual threshold (Vt) is an effective leakage reduction technique and has been adopted in industry EDA tools. It balances the low-leakage-high-delay high Vt cells and low-delay-high-leakage low Vt cells to minimize leakage under timing constraint. We report three recent projects aiming to make dual Vt design more powerful in design tools. First, we propose a temperature-aware approach that leverages the on-chip temperature variation and takes into account the coupling effects between leakage and temperature to enhance the leakage reduction of any dual-Vt assignment algorithm. Then, we discuss how to conduct simultaneous dual Vt and input vector assignment to further reduce leakage. Finally, we demonstrate how to extend this cell-level technique to transistor-level and integrate into existing design tools.  

 

Bio:

Gang Qu received the B.S. and M.S. in Mathematics from the University of Science and Technology of China, and Ph.D. in Computer Science from the University of California, Los Angeles. He joined the Department of Electrical and Computer Engineering in the University of Maryland at College Park in 2000, where he is currently an Associate Professor. His current research interests include low power system design, wireless sensor network, security and trusted system design, intellectual property reuse and protection. He has published more than 100 journal and conference papers in these areas and won 2 best paper awards. He has served the technical program committee for numerous conferences and is an active reviewer for many scientific journals.