MOSFET compact modeling has gone through the same history as CMOS technology in the past three decades.  As the central link between circuit designers and technology developers, compact models have played a key role in the semiconductor industry for generations of technologies.  As technology scales, the model describing it also evolves, and modeling has become a form of art for capturing the multi-dimensional characteristics of a nanoscale MOSFET, and for designing circuits with millions of transistors as well as their variations from a given technology.  The beauty of the “hand-crafted” mathematical formulations reflects the deep physics understanding of the model developers.  Compact models not only have been used for designing IC chips, they also provide a very good training ground for device and technology engineers to catch up with the evolving CMOS technology.

This talk presents the motivation and philosophy behind the development of a compact model (Xsim) for unification of MOSFET models with the unified regional modeling (URM) approach.  It is based on unified regional surface-potential solutions for bulk-MOS, which can be extended to generic double-gate (including SOI and nanowire) MOSFETs with common/independent-gate biasing and with/without body contact.  The DC/AC model is physically scalable in geometry/bias as well as in body thickness and doping, encompassing partial/full-depletion and volume/strong inversion. New paradigm shift in “ground-referencing” and “source/drain by label” provides complete Gummel symmetry while allowing physical modeling of asymmetric devices, which also provides easy extension to include contact effects for modeling pn-junction as well as Schottky-barrier (SB) and dopant-segregated Schottky (DSS) source/drain.  The core model is directed towards modeling emerging devices and technologies in one unified framework without duplicating efforts, which also provides seamless transitions among various device structures and operations, with selectable accuracy for simulation and verification of future-generation ULSI circuits.

Dr. Zhou Xing obtained his B.E. degree in electrical engineering from Tsinghua University, Beijing, China in 1983, M.S. and Ph.D. degrees in electrical engineering from the University of Rochester, Rochester, NY in 1987 and 1990, respectively.  He is currently a tenured faculty in the School of Electrical and Electronic Engineering (EEE), Nanyang Technological University (NTU), Singapore, and Program Director of the Computational Nano-Electronics Group of EEE at NTU.  His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development.  His recent research mainly focuses on nanoscale CMOS compact modeling and technology/device simulations.  He was a Visiting Fellow at the Center for Integrated Systems, Stanford University during 1997 and 2001, a Visiting Professor at Hiroshima University in January 2003, and a Visiting Professor at Universiti Teknologi Malaysia in May 2007.  He is the Founding Chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference and Trade Show since 2002.  Dr. Zhou is an elected member of the IEEE EDS Administrative Committee (AdCom) in 2004–2009 and 2011–2013.  He is currently Chair of the EDS Asia Pacific Subcommittee for Regions/Chapters (SRC-AP) and a member of the EDS Compact Modeling, Membership, Publications, and Educational Activities committees.  He has been a Senior Member of IEEE since 1999, an EDS Distinguished Lecturer since 2000, and an Editor for the IEEE Electron Device Letters since 2007.