Abstract:

As we move to higher levels of integration, it is clear that power and
energy efficiency are the most formidable barriers. A chip built out of 1000
cores requires fundamentally rethinking the whole compute stack from the
ground up for energy efficiency. Often, energy efficiency is in direct
conflict with resilience. In this talk, I will describe some of the
architecture technologies that we are exploring, based on low voltage
operation and streamlined architectures.

BIO:

Josep Torrellas is a Professor of Computer Science and (by courtesy)
Electrical and Computer Engineering at the University of Illinois at
Urbana-Champaign (UIUC). He is a Fellow of IEEE and ACM. He is the Director
of the Center for Programmable Extreme-Scale Computing, a center funded by
DARPA, DOE, and NSF that focuses on architectures for extreme energy and
power efficiency. He also directs the Intel-Illinois Parallelism Center
(I2PC), a center created by Intel to advance parallel computing in clients.
He has made contributions to parallel computer architecture in the areas of
shared-memory multiprocessor organizations, cache hierarchies and coherence
protocols, thread-level speculation, and hardware and software reliability.
He received a Ph.D. from Stanford University.