Abstract:

The silicon physical unclonable functions (PUF) measure uncontrollable variations of the integrated circuit fabrication process to facilitate chip authentication and other security related applications. One of the most popular silicon PUF structures is the ring oscillator (RO) PUF; however, the lack of reliable and efficient secret extraction schemes causes very high hardware implementation cost, diminishing its practicality.

 

In this talk, we first propose a temperature-aware cooperative approach to enhance the hardware utilization. The basic idea is to accept the unreliable bits generated by the ring oscillators as long as we can find means to convert them to reliable bits. Then we report a longest increasing subsequence-based grouping algorithm to maximize the secrecy Extraction power of RO PUF. We also introduce a hybrid architecture for RO PUF and study its hardware cost and delay. Finally, we present the results that validate our claims by a proof-of-the-concept FPGA-based implementation.    

 

Bio:

Gang Qu received the B.S. and M.S. in Mathematics from the University of Science and Technology of China, and Ph.D. in Computer Science from the University of California, Los Angeles. He joined the Department of Electrical and Computer Engineering in the University of Maryland at College Park in 2000, where he is currently an Associate Professor. His current research interests include low power system design, wireless sensor network, security and trusted system design, intellectual property reuse and protection. He has published more than 100 journal and conference papers in these areas and won 2 best paper awards. He has served the technical program committee for numerous conferences and is an active reviewer for many scientific journals.