摘要：

In order to understand the limits of interconnect scaling, it is necessary  to study intrinsic properties of various materials used in the fabrication  of interconnects.  Time dependent dielectric breakdown (TDDB) is one of the  key material properties to consider when it comes to barrier and/or low-k  scaling.  However, TDDB tests are traditionally performed on a damascene  structure, which requires leading edge processes to fabricate especially  when a new low-k material or small pitch is involved.  This high threshold  not only increases the R&D costs but also prevents companies, universities  and research institutions from making more contributions to barrier/low-k research and development.  Furthermore, TDDB results from damascene are  strongly influenced by process issues in low-k patterning and Cu CMP.  The  results can only indicate the quality of the process integration but do not necessarily reflect intrinsic properties of barrier/low-k.  Clearly, there  is an urgent need to develop a novel test structure which can reveal  intrinsic TDDB performance of barrier/low-k and meanwhile does not require

leading edge processes to fabricate.  Such a structure has been successfully  developed recently based on a planar capacitor design.  The applications and  key results of this test structure will be presented and discussed in this  talk.

简历：

Larry Zhao joined Intel Corporation in 2002 and is currently working at  IMEC, Belgium as an assignee from Intel.  At IMEC, he manages and  coordinates all Intel’s interconnect related research projects.  One of his  key interests is to study intrinsic properties of barrier/low-k.  His work  has received recognitions from the semiconductor industry.  He has been  invited to give talks at 2009 Semicon Japan, 2010 MAM conference in Europe, and 2010 Semicon China and nominated for an invited talk at 2010 IITC in San  Francisco, California.  He is also a co-author of an invited talk at 2010  MRS.