Abstract:

In this talk we show high throughput architectures suitable for FPGA implementations for core router functions. We first develop a SRAM based architecture for the classic packet routing problem. The archiecture can be modularly scaled by using large external SRAMs to support large routing tables. The design exploits the features of state of the art FPGAs to use the on chip resources such as BRAMs to compactly store and access the routing data structure. Our implementations show a state of the art FPGA device can support 200K+ prefixes and achieve 100Gbs+ worst case throughput. Using a single SRAM external stage, the architecture can support the same throughput with 2M prefixes. We also extend the idea for multidimensional packet classification. Using a single state of the art FPGA device, the design can support a rule set having 62K distinct entries. Our architecture can also be easily partitioned, so as to use external SRAM to handle even larger rule sets (up to 512K distinct entries), while maintaining 228 mega packets per second (MPPS) throughput. Furthermore, for a rule set of up to 5K entries, the architecture can be duplicated to achieve a throughput of 2 giga packets per second (GPPS). Use of SRAMs as opposed to TCAMs leads to significant power savings.

We also develop a compact architecture for intrusion detection using regular expression rules. The architecture is based on non deterministic finite automaton (NFA) and is well suited for FPGA implementation leading to high clock rate designs. Our architecture permits spatial cascading to accept multiple input characters in each cycle. It achieves 10Gbps+ throughput performance for a representative collection of regular expressions from the Snort rule set. Our approach achieves over 14x throughput efficiency (Gbps*states/LUT) compared with implementations based on automatic synthesis tools.

Biography：

Viktor K. Prasanna (ceng.usc.edu/~prasanna) is Charles Lee Powell Chair in Engineering in the Ming Hsieh Department of Electrical Engineering and Professor of Computer Science at the University of Southern California. He is the executive director of the USC-Infosys center for advanced software technologies. He is also a member of the USC-Chevron Center of Excellence for Research and Academic Training on Interactive Smart Oilfield Technologies. His research interests include parallel and distributed systems including networked sensor systems, embedded systems, configurable architectures and high performance computing. He has served on the editorial boards of the Journal of Parallel and Distributed Computing, Proceedings of the IEEE, IEEE Transactions on VLSI Systems, and IEEE Transactions on Parallel and Distributed Systems. He served as the Editor-in-Chief of the IEEE Transactions on Computers during 2003-06. He was the founding Chair of the IEEE Computer Society Technical Committee on Parallel Processing. He is a Fellow of the IEEE and the ACM.