Abstract:
As technology scales, interconnects become one of the most critical factors in determining the digital system speed and power consumption. Transmission lines offer the potential to break the wall that blocks the interconnect performance. First, the transmission line can allow the signal to travel at the speed of light in the medium. Second, the signal toggles as wave instead of enforced electronic charges and thus saves power. In order to make the transmission line competitive in practice, we face the following challenges.

1. The signal attenuation: The bound of signal attenuation determines the dimensions of the wires. The received signal should be kept large enough to be immune from crosstalk and noise.
2. The intersymbol interference: We need to solve the intersymbol interference caused by the signal distortion. We can preemphasize the signal at the driver or equalize at the receiver to increase the magnitude in high frequency band. The compensation can be carried out by active devices or even passive RLC components to save power.
3. The performance of drivers and receivers: The delay and bandwidth of the drivers and receivers contribute to the overall performance of the interconnect. The required conversion at the drivers and receivers contributes to the delay and bandwidth limit.
4. The scalability: We would like to shrink the transmission lines to increase the throughput of the communication in a given physical space. The cross section is related to the length of the wire. We can use inserted transceivers to reduce the wire length. The insertion will then scale the cross section of the wires at the expense of extra power consumption.

We present a transmission line approach to improve communication speed with significant power reduction. An optimization flow is developed based on eye-diagram prediction and sequential quadratic programming. The scalability of the scheme is investigated for technology nodes from 90nm to 22nm.
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Speaker: Chung-Kuan Cheng, Computer Science and Engineering Department, UC San Diego. Chung-Kuan Cheng received the Ph.D. degree in Electrical Engineering and Computer Sciences from University of California, Berkeley in 1984. From 1984 to 1986, he was a senior CAD engineer at Advanced Micro Devices Inc. In 1986, he joined the University of California, San Diego, where he is a Professor in the Computer Science and Engineering Department, and an Adjunct Professor in the Electrical and Computer Engineering Department. He served as a chief scientist at Mentor Graphics in 1999. He is a recipient of the best paper awards, IEEE Transactions on Computer-Aided Design in 1997, and in 2002, the NCR excellence in teaching award, School of Engineering, UCSD, 1991, an IEEE Fellow in 2000, and IBM Faculty Awards in 2004, 2006, and 2007.